1. Field of the Invention
The present invention relates to a microcomputer operable under microcode control, and more particularly to a microcomputer capable of branching to different microcode routines among instructions without causing any delay in branch timing.
2. Description of the Prior Art
FIG. 4 is a block diagram illustrating a typical arrangement of a microcomputer operable under microcode control.
As shown in the figure, a ROM 1 (memory) composed of a control ROM1 a and a sequence ROM 1b stores microcode. A branch controller 2 issues an 8 bit address signal A.sub.0 to A.sub.7, i.e., an addressing bit signal for specifying the address of each microcode stored in the ROM 1. The control ROM 1a and the sequence ROM 1b issue signals in one to one correspondence to those addresses for executing those designated microcodes. The control ROM 1a stores CPU control information and delivers that information to a CPU 4 through a latch 3, thereby permitting the CPU to execute the predetermined operation. In addition, the sequence ROM 1b transmits back to the branch controller 2 an address signal A.sub.7 ' to A.sub.0 ' for the next microcode to be executed in succession and a branch control signal S.
Instruction register 5 provides an 8 bit instruction code O.sub.7 to O.sub.0 to an instruction decoder 6. The instruction decoder 6 decodes the instruction code O.sub.7 to O.sub.0. In succession, the decoded signal is sent to the branch controller 2, which in turn sends the address of the first microcode required for the execution of that instruction to the ROM 1 through an address decoder 7. The instructions thereafter are executed by permitting the microcode itself to indicate its address to be executed in succession by the sequence ROM.
In what follows, operation of the microcomputer of FIG. 4 will be described with reference to FIG. 5 which illustrates a timing chart for the microcomputer. Designated here at .PHI..sub.1 is a reference clock for the microcomputer. With the end of the instructions being executed, the next instructions are fetched, and the instruction code O.sub.7 to O.sub.0 is entered in the instruction register in a period A, in which the clock is low, .PHI..sub.1 ="L". The instruction code O.sub.7 to O.sub.0 is decoded in the same period A, and the decoded signal is transmitted to the branch controller 2. The branch controller 2, which receives the decoded signal, determines the address A.sub.7 to A.sub.0 of the first microcode for executing this instruction, and transfers the address signal A.sub.7 to A.sub.0 to the ROM 1 in one clock cycle (periods B and C in FIG. 5) beginning when the clock is high .PHI..sub.1 ="H". The control ROM 1a then transmits a control signal to the CPU4 through the latch 3 during periods C, D, and E for causing the CPU4 to execute the operation corresponding to the microcode. In the meanwhile, the sequence ROM1b transmits the address signal A.sub.7 ' to A.sub.0 ' of the next microcode to be executed in succession along with a branch control signal S back to the branch controller 2 during the periods C and D. The branch controller S decodes these signals A.sub.7 ' to A.sub.0 ' and S, and transmits the address of the next microcode to be executed in succession to the ROM 1 during the periods D and E. As this sequence is repeated, one instruction is executed over several cycles.
How an execution sequence of the microcode is branched will now be described. FIG. 6 illustrates part of the branch controller 2. The reference symbols P71, P72, P73, P74 . . . , P01, P02, P03, and P04 designate P channel MOS transistor. The reference symbols A.sub.7i, A.sub.7i, . . . , A.sub.7n, A.sub.7n, . . . , A.sub.0n, A.sub.0n designate n channel MOS transistors, to the gates of which are respectively applied to address signals A.sub.7 ', A.sub.7 '.about.A.sub.0 ', A.sub.0 ' from the sequence ROM 1b. The reference symbols n.sub.71, n.sub.72, n.sub.73, n.sub.74, . . . , n.sub.03, n.sub.04 designate n channel MOS transistors, which are respectively switched on by branch control signals E.sub.1 to E.sub.n. The address signal A.sub.7 ' to A.sub.0 ' and the branch control signal S are decoded in the period C of .PHI..sub.1 ="L" in the timing chart shown in FIG. 5. When the associated execution sequence is not branched, the signal E.sub.n in the circuit diagram of FIG. 6 changes to "H" in the period D of .PHI..sub.1 ="H". This permits A.sub.7 ' to A.sub.0 ' to be transferred as they are to A.sub.7 to A.sub.0 as the address of the next microcode. On the other hand, when the execution sequence is branched, one of the decoder signals E.sub.1 E.sub.n-1 of the branch control signal S changes to "H" in the period D. For example, once the signal E.sub.i changes to "H", the execution sequence is branched to any of A.sub.7 ' to A.sub.1 ' a microcode and A.sub.7 ' to A.sub.1 ' at the address O.sub.0, and a microcode at an address O.sub.0, by the least significant bit O.sub.0 of the instruction code.
FIG. 7 simply illustrates this situation. The advantage of such use of the branch is to save on the capacities of the control ROM and the sequence ROM by permitting various different instructions or different operands of the same instructions to own jointly a common microcode in the execution sequence thereof and branch when they encounter any non-common microcode.
However, such a branch system of the microcode in prior microcomputers suffers from the following problems: As shown in the timing chart of FIG. 5, information for the branch must be securely determined in the period of .PHI..sub.1 ="L", and the timing for the branch must be delayed by one cycle provided the information is determined in the period D of .PHI..sub.1 ="H". Accordingly, any additional required microcode will be delayed correspondingly. Furthermore, provided the timing for the branch is delayed by one cycle, any circuit to detect that delay necessarily results in a more complicated branch controller.